The invention relates to semiconductor devices, including DRAM memory devices. In particular, the invention relates to such devices having buried single-sided conductors and methods for their formation.
Large DRAMs are silicon based. Each DRAM cell typically includes a single MOS field effect transistor, a charge transfer device, with one of its source/drain diffusions connected to a storage capacitor. The other of the source/drain diffusions of the MOSFET typically is connected to a bit line. The gate typically is connected to a word line.
The DRAM cell operates by storing a charge on the capacitor for a logic 1 and not storing any charge for a logic 0. To maintain stable circuit operation, the capacitance must be large enough and the charge transfer device must retain the stored charge, to yield a sufficient signal-to-noise ratio.
Continued miniaturization in the IC industry is driving a paradigm shift towards devices with vertical MOSFET access transistors. The long term trend in DRAM technology is toward storage elements with stacked capacitors (STC). These trends were described in the disclosure of application Ser. No. 09/597,887, filed Jun. 19, 2000 and assigned to the assignee of the present application. In order to successfully fabricate vertical MOSFET access transistors, robust methods of fabricating single sided conductor elements must be developed. The methods described in the prior art make use of photoresist materials to fill structures, photoresist CMP, lithography exposure to perform partial expose within a narrow topography region -techniques that are quite unproven, may not be well-controlled, and probably lack robustness for under 120 nanometers ground rule manufacturing for which they are intended. The present invention described herein improves upon the prior art and overcomes the problems encountered there. Further, the inventive method employed here does not make use of any additional lithography steps and it is inherently self-aligned, obviating any lithography alignment and overlay issues.
In the prior art, a double-sided strap is temporarily formed, allowing out-diffusion to occur on the side of the storage trench which should not contain a strap. This leads to the problem of undesirable interactions between adjacent devices. The present invention teaches a novel method of cutting the strap early in the process on one side only, thereby enabling controlled dopant out-diffusion from one side of the strap, while preventing any dopant out-diffusion from the other side of the strap.
Although the present invention is described in its current embodiment as being used in a DRAM cell, it is applicable to other integrated circuits where buried conductor elements with single-sided contact need to be fabricated. Further, the present invention also teaches a method to form sub-minimum feature size structures without any additional lithography steps (a maskless process or a self-aligned process).
According to the invention, there is provided a semiconductor device fabricated as a trench capacitor cell having first and second sides. One side of the trench is filled with dielectric thus defining the resultant device into conductive and non-conductive sides. The conductive side of the trench has formed within it a buried conductive layer, a single sided strap formed above the conductive layer, and gate oxide formed above the strap. The strap forms a first electrode and the substrate, Si, forms a second electrode.
According to another aspect of the invention, angled ion implantation is used to dope a protective layer of polysilicon above the trench thus defining portions of the trench sensitive and insensitive to subsequent etching steps. Thus subsequent etching and deposition may occur without requiring expensive and time consuming lithographic operations.
According to another aspect of the invention, a structure and process especially suitable for vertical MOSFETs and stacked storage capacitor elements.
According to another aspect the invention relates to a method of fabricating a trench capacitor cell having a single-sided buried conductor comprising:
providing a semiconductor substrate successively layered with pads of SiN, hardened oxide, and SiN and having a bitline trench pattern etched therein;
providing trench liner;
filling the trench with dielectric;
pulling back top SiN layer;
conformally layering polysilicon over top SiN layer;
performing angled boron implantation wherein the implantation divides the trench into first and second sides;
etching undoped polysilicon from above the first side of the trench;
etching oxide fill layer from the first side of the trench;
etching exposed the first SiN liner from the first side of the trench;
forming a BBL conductor layer in the first side of the trench;
etching exposed oxide liner from the first side of the trench;
etching exposed the second SiN liner from the first side of the trench;
etching exposed the first SiN liner from the first side of the trench;
growing gate oxide on exposed Si surfaces;
forming gate oxide layer; and
forming dielectric layer.
Furthermore, the invention provides a novel method for defining sub-lithographic features.
An advantage according to an aspect of the invention is a means for accomplishing controlled, anisotropic out-diffusion of dopant from a strap. Additionally, means are provided for cutting a strap on only one of two sides.
Moreover, the invention provides a novel structure and method for connecting wiring structures (wordlines) to gate conductors.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.